One current challenge to micro- and nanoelectronics is the understanding of stress-related phenomena in metallization. Stresses arising in on-chip and 3D metal interconnects and in the surrounding materials due to thermal mismatch, microstructure changes or process integration as well as electromigration can lead to degradation and failure of microelectronic products. The implementation of low dielectric constant materials into the inlaid copper backend-of-line process has brought new challenges for process integration and reliability. Understanding stress-related phenomena in new materials used for 3D integration and packaging, particularly using through silicon vias and microbumps, is critical for future microelectronic products. The Proceedings summarize new research results and advances in basic understanding of stress-induced phenomena in metallization. In addition to experimental studies, modelling and simulation capabilities are demonstrated to evaluate the effect of stress on product performance and reliability. Stress-related phenomena in 3D IC interconnects are covered too.